High-performance audio CT∆ΣMs have typically been realized using single-loop techniques. Further, many of the designs that achieve state-of-the-art performance have employed single-bit (rather than multibit) quantizers, since a multibit ADC results in increased power dissipation in the clock distribution network. Also, a multibit feedback DAC needs to be linearized, which usually complicates design, and increases power dissipation. In this work, design of a cascaded continuous-time ∆Σ modulator based on single-bit ADCs is discussed.

A first-order single-bit CT∆ΣM employing FIR feedback is cascaded with a 1-bit second-order ∆Σ back-end to achieve a modulator with maximum stable amplitude (MSA) that is close to full-scale, and a third-order overall noise transfer function (NTF). FIR feedback is used in the input-stage to reduce clock- jitter sensitivity, improve linearity, and reduce chopping artifacts. This work shows that in a MASH ADC, FIR feedback has the additional benefit of filtering the error waveform of the first-stage that is fed into the second stage. This principle is applied to an audio continuous-time delta-sigma modulator. A prototype chip, fabricated in 180 nm CMOS to demonstrate the principle, achieves 100.9 dB SNDR in a 24 kHz bandwidth, and dissipates 265 μW. The resulting Schreier Figure-of-Merit is 180.5 dB.