Increased source-drain tunneling (SDT) at smaller channel lengths has emerged as a major roadblock to further scaling down of transistor dimension. The problem is particularly severe for low power (LP) devices, with OFF-state current limited to 1nA/µm, practically ruling out the use of high-mobility materials in the channel. Increased SDT in these materials implies that channel material options beyond silicon are limited for LP devices. The reduced effectiveness of conventional performance improvement techniques like using embedded source/drain stressor or strained capping layers at small gate pitches makes it challenging to achieve the required OFF-current specification while attaining suitable ON/OFF ratios for good switching performance. In this work, we investigate the performance of Silicon-Germanium (SiGe) channel nanowire pMOSFETs at gate length of 10 nm, with varying mole fractions of Ge. Our results obtained using rigorous quantum transport simulations show that using SiGe as channel material over Si, does not result in significant performance improvement over Si-based LP devices. In the 2nd part of this work, we discuss the implementation of a fully atomistic quantum transport solver to accurately model the behavior of deeply scaled nanowire pMOSFETs. Using this atomistic transport solver, we study the ultimate scaling potential of Si nanowire pMOSFETs down to a channel length of 5nm while scaling down the supply voltage to sub- 500 mV regime. Our results show that by suitably choosing the channel crystallographic orientation, it might be possible to scale down Si nanowire pMOSFETs to sub-10 nm gate lengths for LP devices while ensuring good ON/OFF switching ratios.