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Improved Design of Continuous-Time Delta-Sigma Modulators Using FIR Feedback

Improved Design of Continuous-Time Delta-Sigma Modulators Using FIR Feedback

Date21st Sep 2020

Time10:00 AM

Venue https://meet.google.com/gjj-ysyv-fcp

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Details

Continuous-time Delta-Sigma Modulators (CT∆ΣMs) are attractive choice for analog-to-digital conversion due to their resistivity input impedance and implicit anti-aliasing. Moreover, the unity-gain bandwidth required of the opamps in a continuous-time modulator is much lower than that in the case of a discrete-time version. This results in low-power requirement. It turns out that using a single-bit quantizer results in low-power operation. In applications that target low speeds, flicker noise from the first integrator is very problematic. Another problem is that the high-order delta-sigma loops that use a single-bit quantizer (to save power) suffer from a reduced maximum-stable amplitude (MSA). We analyze and address both these problems and demonstrate the efficacy of the solutions with measurements from two fabricated chips. We will see how an FIR feedback can be used to address both these problems.



Chopping is a traditional and effective way of addressing flicker noise in amplifiers. Unfortunately, chopping in a CT∆ΣM leads to aliasing of shaped quantization noise into the signal band, and degrades performance. In the first work, we analyze the mechanism of shaped-noise aliasing in an OTA-RC integrator that uses a two-stage feedforward-compensated OTA, and show that aliasing can be largely mitigated by using an FIR feedback DAC with its zeros placed at multiples of twice the chopping frequency. The theory is borne out by measurement results from a single bit CT∆ΣM which achieves a peak SNDR of 98.5 dB in a 24 kHz bandwidth while consuming only 280μW from a 1.8 V supply. Realized in a 180nm CMOS technology, it achieves a 1/f noise corner of about 3 Hz when chopped at fs/24.



The second work deals with an architecture of a multi-stage noise shaping (MASH) converter. We combine a first-order one-bit CT∆ΣM employing FIR feedback with a one-bit second-order∆Σ back-end to achieve a modulator with maximum-stable amplitude (MSA) that is close to full-scale, and a third-order overall noise transfer function (NTF). We show that in a MASH ADC, FIR feedback has the additional benefit of filtering the error waveform of the first-stage that is fed into the second stage. We apply the principle to an audio continuous-time delta-sigma modulator. A prototype chip, fabricated in 180nm CMOS to demonstrate the principle, achieves100.9 dB SNDR in a 24 kHz bandwidth, and dissipates 265 μW. The resulting Schreier Figure-of-Merit is 180.5 dB.

Speakers

Mr.Sujith Kumar B(EE13D208)

Electrical Engineering