With the advent of multi-core processors, the need for reliable and scalable infrastructure for on-chip communication has increased. Network-on-Chip (NoC) was proposed as an alternative to bus based communication in microprocessor. The performance of NoC is measured in terms of average packet latency, throughput and power consumption. Our aim is to study the performance of NoC under different circumstances, in this regard we propose a mathematical model based on queuing networks that can be used to analyze the performance of NoC. Part of our research focusses on modelling the packet flow in an NoC using generalized open feed-forward queuing network. We then use the model to analyze the performance of NoC for different traffic patterns, routing algorithms, injection processes, number of virtual channels, packet size and buffer size. The numerical results obtained are validated with results from Booksim simulator. In the second part of our research we focused on studying the power consumption in an NoC. The main components of an NoC router are buffer, crossbar, allocator and clock tree. Initially we studied the power consumption of internal components of an NoC router using DSENT simulator. We learned that on an average 66% of the power is consumed by the buffers and 22% of the power is consumed by the crossbar. Next we studied the power consumption of the overall NoC under different configurations containing different traffic patterns, routing algorithms, network sizes. We used power and throughput per watt metrics to analyze the power consumption of NoC under several configurations. Often there is tradeoff between power and performance. For example under random traffic the power consumption with XY routing is high but the performance is better with XY. With shuffle traffic power consumption of West First routing is high but performance is better with XY.