Turbo codes are an important component of several wireless communication systems, and are usually decoded using iterative decoders. They also consume a significant portion of the power consumed by the system, and Several efforts have been proposed to address this issue. Since these decoders work on inputs across a wide range of operating conditions (signal to noise ratio), it is desirable if the decoder could exploit this behaviour to relate the power consumption to the operating scenario. In this work, we have proposed scalable bit width architectures for the BCJR decoders that are components of the Turbo decoder, in which the bit width can be dynamically reduced based on the operating condition and the SNR requirement. We have proposed the concept of dynamic bit width adaptation across iterations in which the bit width for the state metric storage is varied as we move forward in the iterations without any impact to the overall performance in terms of block error rate (BER) and Average Iteration Number (AIN). We also proposed state metric encoding to reduce the bit width requirement for the storage memory in which we dynamically scale the state metric array in each cycle so that only the relevant information bits are stored in the memory along with the scale factor. We also proposed scalable memory architecture whose power consumption can be scaled down based on the bit width required for the given iteration. The proposed scalable bit width BCJR decoder is implemented in RTL and power consumption of the BCJR decoder is estimated for different bit widths using the synthesis netlist (45nm library). Based on simulations of the decoder, we show how the total energy consumed can be reduced significantly, and can be made to exploit the operating conditions to get up to 32% energy reduction.