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Area and Power Efficient Control Techniques for Voltage Regulators using Mixed-Mode Time-Based Signal Processing

Area and Power Efficient Control Techniques for Voltage Regulators using Mixed-Mode Time-Based Signal Processing

Date16th Feb 2024

Time11:00 AM

Venue ESB 210B

PAST EVENT

Details

With an effort to integrate more hardware features on a mobile device, there is a tremendous increase in the number of power supplies used in smartphones and tablets. This power supply demand is catered by voltage regulators which could be either linear low-drop out (LDO) regulator or switching dc-dc converter. Conventional voltage-based regulators require large on or off-chip passive components and suffer from trade-offs between quiescent power and bandwidth/speed. In an effort to overcome the limitations with conventional voltage-based regulators, a highly integrated, continuous time controller using time-based signal processing is presented. By using time as the processing variable, it eliminates the need for wide bandwidth error amplifiers, large on-chip compensation capacitor, PWM modulator and high resolution ADC while preserving the benefits of both analog (high accuracy, low quiescent current) and digital (low voltage operation, smaller area and process scalability) controllers. The versatility of the proposed time-based control (TBC) technique is demonstrated by implementing two different types of voltage regulators, PMOS Low Drop-Out regulator (PLDO) and NMOS Low Drop-Out Regulator (NLDO).

A low quiescent current Master-Slave Domino Controlled PMOS-Low Dropout Regulator (MSD-PLDO) is proposed using TBC technique. The LDO is designed using domino control which automatically increases or decreases the drive strength based on the load current while maintaining high current efficiency. The proposed LDO architecture is fully scalable and can be easily scaled up for higher load currents with almost no additional design efforts. Implemented in TSMC-180nm CMOS process, it uses only 3pF of on-chip compensation capacitor and consumes a quiescent current of 15μA. For an input of 1.2 V and LDO output of 0.9V to 1.1V, it drives a maximum load current of 50mA. The settling time of

Speakers

Mr. Abirmoya Santra (EE16D040)

Electrical Engineering