The design of a multi-hit multi-channel time-to-digital converter (TDC) for the India-based neutrino observatory was presented in Seminar-I. The mixed signal implementation of the TDC necessitates rigorous verification of the interaction between the digital and analog blocks. To reduce simulation run time, the analog/custom blocks in the design were reduced to logic level models in Verilog while retaining the required accuracy. A behavioral-level TDC model that has minimal common algorithm with the implemented system is developed to facilitate quicker verification of the simulation results. With the help of these models, the simulation and verification of 600 test cases were completed in less than 9 hours, compared to several days required for the mixed signal simulation for a single test case.

In the second part of the talk, we shall look at the challenges faced while stabilizing the TDC resolution using a delay-locked loop. Static phase offset in a DLL affects the TDC resolution and linearity. A novel technique for static phase offset reduction suitable for low bandwidth delay locked loops is proposed. Analysis of the proposed method shows an offset reduction at least by a factor of 2. Monte Carlo simulations with random process and mismatch variations show that the offset improves from 19.9 ps in the conventional technique to 1.7 ps in the proposed technique.