A Multi-Hit Multi-Channel Time-to-Digital Converter for the India-based Neutrino Observatory
Date28th Aug 2020
Time10:30 AM
Venue Google Meet
PAST EVENT
Details
A time-to-digital converter (TDC) is a circuit that can measure time intervals with very high resolution. This thesis presents the design of a multi-channel time-to-digital converter designed for the iron calorimeter detector in the India-based neutrino observatory. The TDC records the time instants at which a particle of interest is sensed within the detector, thereby aiding the track reconstruction of the particle. The TDC has a resolution of 125ps, dynamic range of 65.5us, and can store the timestamps of the latest 4 events in each channel. The TDC has 17 hit channels and 1 trigger channel, and is compatible with a trigger-based data acquisition system. The TDC core consists of a delay chain stabilized by a delay-locked loop (DLL) and synchronous counters. Circuit nonidealities that affect the TDC performance, such as incorrect DLL locking, mismatches in devices, skew between the coarse and fine TDC, and duty cycle variation in the clock phases are analyzed, and the solutions are discussed. Thorough system-level verification of this design proved to be a challenge due to the long simulation run times. By modeling the analog circuits in Verilog, full system simulation run-time was reduced to 1min. This thesis reviews the theory on how timing precision is defined for a single-shot TDC and explains how the TDC characterization test plan can be devised based on the jitter in the system. The TDC prototype designed in 0.13um CMOS process, achieves a single-shot precision better than 65ps. The measured differential nonlinearity (DNL) varies from -0.27LSB to 0.21LSB, while integral nonlinearity (INL) varies from -0.19LSB to 0.25LSB. The TDC occupies an active area of 3.72mm2 and consumes 3.4mW per channel. Static phase offset is one of the delay-locked loop nonidealities that affects the linearity of a high-resolution TDC. We propose a new technique that reduces the offset due to both PFD and the charge pump without actually chopping the latter. Analysis of the proposed method shows an offset reduction at least by a factor of 2. Monte Carlo simulations with random process and mismatch variations show that the offset improves from 19.9ps in the conventional technique to 1.7ps in the proposed technique.
Speakers
Chithra (EE13D209)
Electrical Engineering