Abstract:

Owing to the failure of Dennard’s scaling, the last decade has seen a steep growth of prominent new paradigms leveraging opportunities in computer architecture. Two technologies of interest are Posit and RISC-V. Posit was introduced in mid-2017 as a viable alternative to the IEEE 754 floating-point format. RISC-V, on the other hand, provides a commercial-grade open-source ISA. In this work, we bring these two technologies together and propose the first configurable Posit Enabled RISC-V core called PERI. This work provides insights on how the Single-Precision Floating Point (’F’) extension and the custom op-code space of RISC-V can be leveraged to support Posit arithmetic. We also present the implementation details of a parameterized and feature-complete Posit Floating Point Unit (FPU). The configurability and the parameterization features of this unit enable generation of optimal hardware which caters to the accuracy and energy/area trade-offs imposed by the applications, a feature not possible with IEEE-754 implementation. The posit FPU has also been integrated with the RISC-V compliant SHAKTI C-class core as an execution unit and/or as an accelerator. To further leverage the potential of Posit, we enhance our Posit FPU, with minimal overheads, to support two different exponent sizes (with posit-size being 32-bits) thereby enabling multiple-precision at run-time. In order to provide a complete software stack support, we enhance the GNU C Compiler with support for Posit thus enabling C programs to be directly compiled and executed on PERI. We provide examples of applications where Posit provides better accuracy compared to IEEE 754.

Regards,
Sugandha Tiwari